Metal-oxide semiconductor (MOS) devices generally include a large number of transistors on a semiconductor wafer. Such transistors each include a source, a gate and a drain. The source and the drain are created on a semiconductor substrate. The gate is separated from both the source and the drain by a dielectric in the form of an electrically nonconductive gate oxide layer, which is disposed on the semiconductor substrate. A voltage applied to the gate produces an electric field that changes the resistivity of the semiconductor substrate, thereby inducing current between the source and the drain.
FIGS. 1A through 1C illustrate steps in a conventional semiconductor fabrication process on a portion of a semiconductor wafer 100. In FIG. 1A, a semiconductor substrate 101 is shown. The substrate 101 has a gate oxide layer 104, which functions as a gate dielectric layer, formed on its upper surface 102. The gate oxide layer 104 may be created in ways well known to those of skill in the art. For example, the gate oxide layer 104 may be composed of silicon dioxide (SiO2) generated by thermal oxidation of surface 102 of the silicon substrate 101. Alternatively, the gate oxide layer 104 may be deposited on the silicon substrate 101 by chemical vapor deposition (CVD). Typical conventional gate oxide layer thicknesses are about 15 to 200 Angstroms.
As shown in FIGS. 1B and 1C, a doped polysilicon (poly) layer 106 is typically deposited over the gate oxide layer 104 in order to provide the material from which a gate electrode may be formed. The doped polysilicon layer 106 can be deposited over the gate oxide layer 104 by in situ doped CVD or undoped CVD followed by implantation and annealing, for example. FIG. 1B shows the wafer 100 with the poly layer 106 on the gate oxide layer 104.
FIG. 1C shows the wafer 100 after the poly layer 106 has been patterned and etched to form a gate electrode 108, according to methods well known in the art. The gate electrode 108 may then be used as a mask in a self-aligned implant process that penetrates through the gate oxide layer 104 to produce doped active source 110 and drain 112 regions in the substrate 101, on either side of the gate electrode 108, thereby forming an MOS transistor.
As semiconductor technology has developed, semiconductor device geometries have been reduced. As a result, the various components that make up a semiconductor have been decreased in size. As device sizes decrease, gate dielectric layers in such devices should correspondingly become thinner. In addition to being more compact in size, thinner gate dielectrics have the advantage of providing more capacitance between the gate electrode 108 and the silicon substrate 101, thereby reducing the voltage at the gate electrode 108 that is required to induce current between the source 110 and the drain 112. Thus, thinner gate dielectrics improve the performance of the device.
A problem, however, with thinner gate dielectric layers is that such layers allow more leakage current. A thinner gate dielectric layer provides a shorter current path between the gate electrode and the semiconductor substrate. The shorter current path results in a correspondingly lower electrical resistance between the gate electrode and the semiconductor substrate. The lower resistance, in turn, allows greater leakage current between the gate electrode and the semiconductor substrate. More specifically, there is greater leakage current between the gate electrode 108 and the source 110 and/or between the gate electrode 108 and the drain 112. Ideally, a MOS transistor and other semiconductor devices have no leakage current.
Leakage current is undesirable because leakage current results in wasted power that requires additional cooling of the device. Another problem caused by leakage current is that device speed is decreased. The leakage current creates an element of random noise in the signal between the source and the drain. In order to detect the signal between the source and the drain with a requisite degree of certainty, the magnitude of the signal must be allowed rise substantially above the level of the noise. The rise of the signal between the source and the drain is not instantaneous, but rather occurs over a non-negligible amount of time. Thus, the higher the signal must rise in order to be detected, the more time it takes to be detected, thereby reducing the overall speed of the device.
Another problem with thinner gate dielectric layers is that, at high temperatures, such layers allow the penetration of gate electrode dopants through the dielectric layers and into the silicon substrate. More particularly, dopants such as boron may penetrate through the gate-electrodes 108, through the dielectric gate oxide layer 104, and into the channels in the silicon substrate 101.
Dopant penetration into the silicon substrate is undesirable because it can lead to hot electron degradation and the reduction of the breakdown resistance of the gate oxide. Such penetration of dopants into the silicon channels causes a depletion of dopants at the interfaces between the gate-electrodes 108 and the dielectric layer 104, and results in a reduction of charge carriers in that region. This charge depletion effect (poly depletion effect) frequently leads to the apparent increase in the electrical thickness of the dielectrics and degrades the performance of the CMOS devices.
Techniques have been developed to address the problems of high leakage current and dopant penetration into the silicon substrate in high performance CMOS devices. For instance, a known improvement in the manufacture of thin gate dielectrics includes forming the thin gate dielectrics of silicon oxynitrides (SiOxNy) having less than 10% nitrogen. Advantages of introducing nitrogen into the thin gate dielectric include reducing boron diffusion into the silicon substrate. Although forming the thin gate dielectrics of silicon oxynitride addresses the problem of dopant penetration into the silicon substrate, it does not solve the other problem of high leakage current.
One of the major requirements of thin gate dielectrics in CMOS devices is that their gate leakage current densities be less than 1 Amp/cm2 at room temperature. The mechanism governing the magnitude of the leakage current for ultra-thin silicon oxynitride at room temperature is Fowler-Nordheim tunneling.
It is desirable for the gate length, i.e., the length L of the gate electrode 108 in FIG. 1C, to be as small as possible in order to minimize the size of the device. Gate lengths of 70 nm have been achieved in “70 nm technology node” transistors. A problem, however, is that the shorter the gate length is, the thinner the dielectric 104 must be in order for the device to have an acceptable level of capacitance. The thickness of the dielectric, in turn, has an inverse relationship with the leakage current. Thus, the thinner dielectric layers associated with shorter gate lengths result in greater leakage current, which is, of course, undesirable. Experimental results have shown that leakage currents are increased by an order of magnitude for every 2 Angstroms reduction in the thickness of the dielectric.
From these experimental results it can be estimated that the continued use of silicon oxynitride gate dielectrics for 70 nm technology node transistors will result in leakage currents above 50 Amp/cm2, which is above the acceptable level of leakage current for 70 nm technology node transistors.
It has been found that the leakage current can be reduced by using a dielectric material including a metal silicate (e.g., ZrxSi1-xO2, HfxSi1-xO2) instead of silicon oxynitride. The metal silicate does not reduce dopant penetration into the silicon substrate, however, with the same effectiveness as does the silicon oxynitride. The metal silicate has a higher dielectric constant (K value) than the silicon oxynitride. A dielectric material with a higher dielectric constant provides correspondingly higher capacitance between the gate electrode 108 and the silicon substrate 101, as is well known in the art. As discussed above, the capacitance has an inverse relationship with the thickness of the dielectric. By using the metal silicate, having a higher dielectric constant, instead of the silicon oxynitride to form the dielectric layer, it is thus possible to form the dielectric layer with a greater thickness, thereby decreasing leakage current, while still maintaining the same dielectric properties, i.e., providing the same capacitance.
One of the important considerations in using silicates is the choice of the ratio between metals and silicon, since this ratio determines the value of the dielectric constant of the silicate. For example, the K value of Hf0.2Si0.8O2, which is a medium K dielectric, is about twice that of silicon oxynitride or SiO2. Thus, a silicon oxynitride dielectric having a thickness of 12-13 Angstroms (which is about the appropriate thickness for a 70 nm node device) can be replaced by an Hf0.2Si0.8O2 dielectric having a thickness of 25 Angstroms. The Hf0.2SiO0.8O2 dielectric can be said to have an equivalent thickness or equivalent oxide thickness (EOT) of 12-13 Angstroms. That is, an Hf0.2Si0.8O2 dielectric having a thickness of 25 Angstroms provides the same capacitance as a silicon oxynitride dielectric having a thickness of 12-13 Angstroms. Such use of a metal silicate dielectric has been demonstrated to be effective in reducing the gate leakage current.
The increased dielectric thickness of 25 Angstroms that is made possible by the use of a metal silicate as the dielectric material is still not sufficient to prevent the penetration of gate electrode dopants through the dielectrics at high temperatures. As mentioned above, introducing nitrogen into silicon dioxide inhibits dopant penetration through the dielectric. It has been found that the degree of dopant penetration through metal silicate dielectrics can also be suppressed by the incorporation of nitrogen into the metal silicates. Thus, the inclusion of both nitrogen and metal in the dielectric material can result in a device having acceptable levels of both current leakage and dopant penetration.
Similar to the role of nitrogen in silicon dioxide, there are certain requirements imposed on both the percentage and the spatial distribution of nitrogen in metal silicates if the performance of the MOS devices is to be acceptable. A low percentage of nitrogen is not sufficient for blocking dopant penetration. Conversely, a high percentage of nitrogen can result in excessive charge trapping. Thus, a first requirement when incorporating nitrogen into a metal silicate dielectric is that the percentage incorporation of nitrogen be within a desired range.
Although a small percentage of nitrogen at the interface between the dielectric layer 104 and the silicon substrate 101 can improve the performance of the devices, too much nitrogen at the interface degrades channel mobility, and hence worsens performance. Thus, a second requirement when incorporating nitrogen into a metal silicate dielectric is that the spatial distribution profile of nitrogen in the dielectrics (i.e., how deeply the nitrogen penetrates into the dielectrics) be controlled.
A third requirement when incorporating nitrogen into a metal silicate dielectric comes into effect when the associated CMOS device is to be included in a triple gate system. A triple gate system is characterized by the co-existence of CMOS transistors with three different thicknesses of gate dielectrics on the same integrated circuit chip. The gate can be formed by depositing and patterning a layer of polysilicon, similar to the polysilicon layer 106, so that the polysilicon layer covers an oxide-coated silicon body on top and both sides. The silicon body is similar to the silicon substrate 101, and the oxide coating is similar to the gate oxide layer 104.
A triple gate system includes three types of CMOS devices on the same integrated circuit, with each type of CMOS device having a different and respective dielectric thickness. The CMOS devices have different dielectric thicknesses because the CMOS devices have different applications and different performance (i.e., capacitance) requirements. That is, some of the devices have lower performance requirements and thicker dielectrics, while others are designed for higher performance and have thinner dielectrics.
Only the CMOS devices having the highest performance requirements include thin gate dielectrics formed exclusively of metal silicates. Some lower performance CMOS devices in the triple gate system include gate dielectrics that are thicker and that have properties providing proven performance reliability, and thus their properties should be preserved.
However, the presence of nitrogen affects the properties of a dielectric. Hence, in order to avoid changing the known and desirable properties of the established thicker gate dielectrics, which are not formed exclusively of metal silicates, additional nitrogen should not be introduced into these established gate dielectrics. Thus, a third requirement when incorporating nitrogen into dielectrics is that nitrogen be preferentially incorporated into the dielectrics formed exclusively of metal silicates instead of into the other thicker gate dielectrics which may al so include silicon dioxide or silicon oxynitride.
There are two known techniques for incorporating nitrogen into semiconductor devices, neither of which satisfies each of the three requirements discuss ed above. The first technique is to introduce nitrogen on bare silicon wafers through NH3 annealing before the deposition of a dielectric layer. A first problem with this approach is that it results in too much nitrogen at the interface between the dielectric layer and the silicon substrate, and thus degrades channel mobility. For this reason, NH3 annealing does not meet the second requirement described above. A second problem with this approach is that nitrogen is indiscriminately incorporated into all of the gate dielectrics. Thus, NH3 annealing also does not meet the third requirement described above.
The second technique involves nitrogen plasma treatment from the top surface of the dielectric. This second technique avoids degrading channel mobility and, when used in conjunction with an annealing process, is potentially capable of incorporating nitrogen selectively. However, it is difficult to control the nitrogen dose. Th us, nitrogen plasma treatment does not meet the first requirement described above. Further, it is also difficult to control the spatial distribution of the nitrogen. Thus, nitrogen plasma treatment also does not meet the third requirement described above.
Although the incorporation of nitrogen into semiconductor devices is known to be beneficial, problems are created by all of the known techniques for implementing such an incorporation of nitrogen into a semiconductor device, as described above. Thus, a continuing need exists for a method of incorporating nitrogen into metal silicate based dielectrics that meets all of the three requirements described above. More particularly, what is needed in the art is a method of incorporating nitrogen into metal silicates that results in a favorable percentage incorporation of nitrogen, that allows the spatial distribution profile of nitrogen in the dielectric to be controlled, and that allows the nitrogen to be incorporated preferentially into dielectrics formed only of metal silicates rather than into the other thicker gate dielectrics.